Core Logic
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$0,+* PLFURQ &026 *DWH $UUD\
Description
DF10x is a family of static, master-slave D flip-flops. SET is asynchronous and active low. Outputs are buffered and change state on the rising edge of the clock.
Logic Symbol
Truth Table
DF10x
DSQ C
Q
SN D C Q QN L XXH L HL ↑ LH HH ↑H L H X L NC NC
NC = No Change
HDL Syntax Verilog.......
