DF031

Core Logic ') ® $0,+*  PLFURQ &026 *DWH $UUD\ Description DF031 is a static, master-slave D flip-flop. SET and RESET are asynchronous and active low. Output is unbuffered and changes state on the rising edge of the clock. Logic Symbol DF031 DSQ C R Truth Table SN L L H H H H RN D C LXX HXX LXX HL ↑ HH ↑ HX L NC = No Change IL = Illegal Q IL H L L H NC Pin Loading Equivalent Load D 1.0 C 1.0 SN 2.1 RN 2.2 Equivalent Gates ................ 9.0 HDL Syntax Verilog .................... DF031 inst_name (Q, D, RN, SN); VHDL...................... inst_name: DF031 port map (Q, D, RN, SN); Size And Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation. Value TBD 18.9 Units nA Eq-load Propagation Delays Conditions: TJ = 25°C, VDD = 5.0V, Typical Process From Delay (ns) To Parameter 1 Number of Equivalent Loads 258 C Q tPLH tPHL 0.65 0.63 0.68 0.68 RN Q tPHL 0.79 0.84 SN Q tPLH 0.14 0.18 Delay will vary with input...