CYDMX128A16

16 K/8 K/4 K × 16 MoBL ADM Asynchronous Dual-Port Static RAM 16 K/8 K/4 K × 16 MoBL® ADM Asynchronous Dual-Port Static RAM CYDMX256A16, CYDMX256B16 CYDMX128A16, CYDMX128B16 CYDMX064A16, CYDMX064B16 ® Features ■ ■ True dual-ported memory block that allow simultaneous independent access ❐ One port with dedicated time multiplexed address and data (ADM) interface ❐ One port configurable to standard SRAM or time multiplexed address and data interface 16 K/8 K/4 K × 16 memory configuration High speed access ❐ 65 ns or 90 ns ADM interface ❐ 40 ns or 60 ns standard SRAM interface Fully asynchronous operation Port independent 1.8 V, 2.5 V, and 3.0 V IOs Ultra low operating power ❐ Active: ICC = 15 mA (typical) at 90 ns ❐ Active: ICC = 25 mA (typical) at 65 ns ❐ Standby: ISB3 = 2 A (typical) Port independent power down On-chip arbitration logic Mailbox interrupt for port to port communication Input Read and Output Drive registers Upper byte and lower byte control Small package: 6 × 6 mm, 100-ball Pb-free BGA Industrial temperature range ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Block Diagram SFEN# IRR/ODR IRR1-IRR0 [note 2] ODR4-ODR0 I/OL15-I/OL8 I/OL7-I/OL0 ADV#L UB#L LB#L Mux'ed Address / Data I/O Control DataL<15..0> Dual Ported Memory Array 16k/8k/4k x 16 DataR<15..0> AddrL<13..0> AddrR<13..0> Mux'ed Address/ Data I/O Control I/OR15-I/OR8 I/OR7-I/OR0 ADV#R UB#R LB#R A13-A0 [note 1] Address Decode Address Decode MSEL CS#L OE#L WE#L BUSY#L INT#L Control Logic CS#R OE#R WE#R BUSY#...