CY7C456

57 CY7C455 CY7C456 CY7C457 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags Features High-speed, low-power, first-in first-out (FIFO) memories 512 x 18 (CY7C455) 1,024 x 18 (CY7C456) 2,048 x 18 (CY7C457) 0.65 micron CMOS for optimum speed/power High-speed 83-MHz operation (12 ns read/write cycle time) Low power — ICC=90 mA Fully asynchronous and simultaneous read and write operation Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags TTL compatible Retransmit function Parity generation/checking Output Enable (OE) pins Independent read and write enable pins Center power and ground pins for reduced noise Supports free-running 50% duty cycle clock inputs Width Expansion Capability Depth Expansion Capability 52-pin PLCC and 52-pin PQFP Functional Description The CY7C455, CY7C456, and CY7C457 are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide. The CY7C455 has a 512-word memory array, the CY7C456 has a 1,024-word memory array, and the CY7C457 has a 2,048-word memory array. The CY7C455, CY7C456, and CY7C457 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Empty flags and generation/checking of parity. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFO...