CY7C331

1CY7C331 fax id: 6016 CY7C331 www.DataSheet4U.com Asynchronous Registered EPLD Features Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent (product term) set, reset, and clock inputs on all registers — Asynchronous bypass capability on all registers under product term control (r = s = 1) — Global or local output enable on three-state I/O — Feedback from either register to the array 192 product terms with variable distribution to macrocells 13 inputs, 12 feedback I/O pins, plus 6 shared I/O macrocell feedbacks for a total of 31 true and complementary inputs High speed: 20 ns maximum tPD Security bit Space-saving 28-pin slim-line DIP package; also available in 28-pin PLCC Low power — 90 mA typical ICC quiescent — 180 mA ICC maximum — UV-erasable and reprogrammable — Programming and operation 100% testable Functional Description The CY7C331 is the most versatile PLD available for asynchronous designs. Central resources include twelve full D-type flip-flops with separate set, reset, and clock capability. For increased utility, XOR gates are provided at the D-inputs and the product term allocation per flip-flop is variably distributed. I/O Resources Pins 1 through 7 and 9 through 14 serve as array inputs; pin 14 may also be used as a global output enable for the I/O macrocell three-state outputs. Pins 15 through 20 and 23 through 28 are connected to I/O macr...