CY7C1522KV18

CY7C1522KV18, CY7C1529KV18 CY7C1523KV18, CY7C1524KV18 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture Features ■ ■ ■ ■ ■ Functional Description The CY7C1522KV18, CY7C1529KV18, CY7C1523KV18, and CY7C1524KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with DDR II SIO (Double Data Rate Separate I/O) architecture. The DDR II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR II SIO has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1522KV18, two 9-bit words in the case of CY7C1529KV18, two 18-bit words in the case of CY7C1523KV18, and two 36-bit words in the case of CY7C1524KV18 that burst sequentially into or out of the device. Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs are tightly matched to the two ou...