CY7C1422AV18 CY7C1429AV18 CY7C1423AV18 CY7C1424AV18
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
Features
36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) 300-MHz clock for high bandwidth 2-Word burst for reducing address bus frequency Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz Two input clocks (K and K) for p...
