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CY7C1241V18

Part Number	CY7C1241V18
Manufacturer	Cypress Semiconductor
Description	36-Mbit QDR-II SRAM 4-Word Burst Architecture
Published	Apr 15, 2011
Detailed Description	CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18 36-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency...
Datasheet	CY7C1241V18 PDF File

Overview

CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18 36-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.
0 Cycle Read Latency) Features • Separate independent read and write data ports — Supports concurrent transactions • 300 MHz to 375 MHz clock for high bandwidth • 4-Word Burst for reducing address bus frequency • Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 750 MHz) at 375 MHz • Read latency of 2.
0 clock cycles • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Echo clocks (CQ and CQ) simplify data capture in high-speed systems • Single multiplexed address input bus latches address inputs for both read and write ports • Se...

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