CY29973

CY29973 3.3V 125-MHz Multi-Output Zero Delay Buffer Features ■ ■ ■ ■ ■ ■ Output Frequency up to 125 MHz 12 Clock Outputs: Frequency Configurable 350 ps max. Output to Output Skew Configurable Output Disable Two Reference Clock Inputs for Dynamic Toggling Oscillator or PECL Reference Input ■ ■ ■ ■ ■ ■ Spread Spectrum Compatible Glitch-free Output Clocks Transitioning 3.3V Power Supply Pin Compatible with MPC973 Industrial Temperature Range: - 40°C to +85°C 52-Pin TQFP Package Table 1. Frequency Table[1] VC0_SEL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FB_SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FB_SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FB_SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FVC0 8x 12x 16x 20x 16x 24x 32x 40x 4x 6x 8x 10x 8x 12x 16x 20x Note 1. x = the reference input frequency, 200 MHz < FVCO < 480 MHz. www.DataSheet4U.net Cypress Semiconductor Corporation Document #: 38-07291 Rev. *C 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Revised September 09, 2008 [+] Feedback CY29973 Logic Block Diagram PECL_CLK PECL_CLK# VCO_SEL PLL_EN REF_SEL D Q TCLK0 TCLK1 TCLK_SEL FB_IN D Q Sync Frz 0 1 Phase Detector LPF VCO 0 1 Sync Frz QA0 QA1 QA2 QA3 QB0 QB1 FB_SEL2 QB2 QB3 MR#/OE Power-On Reset SELA(0,1) SELB(0,1) SELC(0,1) FB_SEL(0,1) SCLK SDATA INV_CLK Output Disable Circuitry 12 2 2 2 2 /4, /6, /8, /10 Sync Pulse Data Generator D Q /2 0 1 D Q D Q /4, /6, /8, /12 /4, /6, /8, /10 /2, /4, /6, /8 D Q Sync Frz QC0 QC1 Sync Frz Sync Frz Sync Frz QC2 QC3 FB_OUT SYNC Pin...