CVDD

&9'' ® Description CVDD is the resistive tie-up to the core VDD bus for all cell inputs. Equivalent Gates ................... 1.0 HDL Syntax Verilog .................... CVDD inst_name (Q); VHDL...................... inst_name: CVDD port map (Q); $0,+*  PLFURQ &026 *DWH $UUD\ CVDD Q Core Logic 3-43 ...