CD74HC4017-EP

CD74HC4017ĆEP HIGHĆSPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS550 − DECEMBER 2003 D Controlled Baseline − One Assembly/Test Site, One Fabrication Site D Extended Temperature Performance of −40°C to 125°C D Enhanced Diminishing Manufacturing Sources (DMS) Support D Enhanced Product-Change Notification D Qualification Pedigree† D Fully Static Operation D Buffered Inputs D Common Reset D Positive Edge Clocking D Typical fmax = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25°C † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. D Fanout (Over Temperature Range) − Standard Outputs . . . 10 LSTTL Loads − Bus Driver Outputs . . . 15 LSTTL Loads D Balanced Propagation Delay and Transition Times D Significant Power Reduction Compared to LSTTL Logic ICs D VCC Voltage = 2 V to 6 V D High Noise Immunity NIL or NIH = 30% of VCC, VCC = 5 V M OR PW PACKAGE (TOP VIEW) 5 1 0 2 6 7 3 GND 1 2 3 4 5 6 7 8 16 VCC 15 MR 14 CP 13 CE 12 TC 11 9 10 4 98 description/ordering information The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson co...