D Qualified for Automotive Applications D Synchronous or Asynchronous Preset D Cascadable in Synchronous or Ripple
Mode
...
D Qualified for Automotive Applications D Synchronous or Asynchronous Preset D Cascadable in Synchronous or Ripple
Mode
D Fanout (Over Temperature Range)
− Standard Outputs . . . 10 LSTTL Loads − Bus Driver Outputs . . . 15 LSTTL Loads
D Balanced Propagation Delay and Transition
Times
D Significant Power Reduction Compared to
LSTTL Logic ICs
description/ordering information
CD74HC40103-Q1 HIGH-SPEED
CMOS LOGIC 8-STAGE SYNCHRONOUS DOWN COUNTER
SCLS547A − OCTOBER 2003 − REVISED APRIL 2008
D VCC
Voltage = 2 V to 6 V D High Noise Immunity NIL or NIH = 30% of
VCC, VCC = 5 V
M PACKAGE (TOP VIEW)
CP MR TE P0 P1 P2 P3 GND
1 2 3 4 5 6 7 8
16 VCC 15 PE (SYNC) 14 TC 13 P7 12 P6 11 P5 10 P4 9 PL (ASYNC)
The CD74HC40103 is manufactured with high-speed silicon-gate technology and consists of an 8-stage synchronous down counter with a single output, which is active when the internal count is zero. The device contains a single 8-bit binary counter. Each device has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the terminal count (TC) output are active-low logic.
In normal operation, the counter is decremented by one count on each positive transition of the clock (CP) output. Counting is inhibited when the terminal enable (TE) input is high. TC goes low when the count reaches zero, if TE is low, and remains low for one full clock period.
When t...