CD54ACT280

Data sheet acquired from Harris Semiconductor SCHS250A August 1998 - Revised May 2000 CD54/74AC280, CD54/74ACT280 9-Bit Odd/Even Parity Generator/Checker Features Buffered Inputs Typical Propagation Delay - 10ns at VCC = 5V, TA = 25oC, CL = 50pF Exceeds 2kV ESD Protection per MIL-STD-883, Method 3015 SCR-Latchup-Resistant CMOS Process and Circuit Design Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption Balanced Propagation Delays AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply ±24mA Output Drive Current - Fanout to 15 FAST™ ICs - Drives 50Ω Transmission Lines Description The ’AC280 and ’ACT280 are 9-bit odd/even parity generator/checkers that utilize Advanced CMOS Logic technology. Both even and odd parity outputs are available for checking or generating parity for words up to nine bits long. Even parity is indicated (∑E output is HIGH) when an even number of data inputs is HIGH. Odd parity is indicated (∑O output is HIGH) when an odd number of data inputs is HIGH. Parity checking for words larger than nine bits can be accomplished by tying the ∑E output to any input of an additional ’AC280, ’ACT280 parity checker. Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE CD54AC280F3A CD74AC280E CD74AC280M -55 to 125 0 to 70oC, -40 to 85, -55 to 125 0 to 70oC, -40 to 85, -55 to 125 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC CD54ACT280F3A CD74ACT280E CD74ACT280M -55 to 125 0 to 70oC, -40 to 85, ...