CD54AC191

CD54AC191, CD54ACT191 Data sheet acquired from Harris Semiconductor SCHS243A October 1998 - Revised May 2000 Presettable Synchronous 4-Bit Binary Up/Down Counter Features Buffered Inputs Typical Propagation Delay - 12.8ns at VCC = 5V, TA = 25oC, CL = 50pF Exceeds 2kV ESD Protection MIL-STD-883, Method 3015 SCR-Latchup-Resistant CMOS Process and Circuit Design Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption Balanced Propagation Delays AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply ±24mA Output Drive Current - Fanout to 15 FAST™ ICs - Drives 50Ω Transmission Lines Description The CD54AC191 and CD54ACT191 are asynchronously presettable binary up/down synchronous counters that utilize Advanced CMOS Logic technology. Presetting the counter to the number on preset data inputs (P0-P3) is accomplished by setting LOW the asynchronous parallel load input (PL). Counting occurs when PL is HIGH, Count Enable (CE) is LOW, and the Up/Down (U/D) input is either LOW for upcounting or HIGH for down-counting. The counter is incremented or decremented synchronously with the LOW-toHIGH transition of the clock. When an overflow or underflow of the counter occurs, the Terminal Count (TC) output, which is LOW during counting, goes HIGH and remains HIGH for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 12). The TC output also initiates the Ripple Clock (RC) output wh...