CD4021BMS

CD4014BMS, CD4021BMS December 1992 CMOS 8-Stage Static Shift Registers Description CD4014BMS -Synchronous Parallel or Serial Input/Serial Output CD4021BMS -Asynchronous Parallel Input or Synchronous Serial Input/Serial Output CD4014BMS and CD4021BMS series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel “JAM” inputs to each register stage. Each register stage is a D-type, master-slave flip-flop. In addition to an output from stage 8, “Q” outputs are also available from stages 6 and 7. Parallel as well as serial entry is made into the register synchronously with the positive clock line transition in the CD4014BMS. In the CD4021BMS serial entry is synchronous with the clock but parallel entry is asynchronous. In both types, entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the PARALLEL/ SERIAL CONTROL input is high, data is jammed into the 8stage register via the parallel input lines and synchronous with the positive transition of the clock line. In the CD4021BMS, the CLOCK input of the internal stage is “forced” when asynchronous parallel entry is made. Register expansion using multiple packages is permitted. The CD4014BMS and CD4021BMS are supplied in these 16 lead outline packages...