DatasheetsPDF.com

BUS-61571-xxxx Datasheet

Part Number BUS-61571-xxxx
Manufacturers Data Device
Logo Data Device
Description MIL-STD-1553 Bc-rt-mt Integrated Terminal
Datasheet BUS-61571-xxxx DatasheetBUS-61571-xxxx Datasheet (PDF)

BUS-61559 SERIES MIL-STD-1553B NOTICE 2 ADVANCED INTEGRATED MUX HYBRIDS WITH ENHANCED RT FEATURES (AIM-HY’er) DESCRIPTION DDC’s BUS-61559 series of Advanced Integrated Mux Hybrids with enhanced RT Features (AIM-HY’er) comprise a complete interface between a microprocessor and a MIL-STD-1553B Notice 2 bus, implementing Bus Controller (BC), Remote Terminal (RX, and Monitor Terminal (MT) modes. Packaged in a single 78-pin DIP or 82-pin flat package the BUS-61559 series contains dual low-power trans.

  BUS-61571-xxxx   BUS-61571-xxxx






MIL-STD-1553 Bc-rt-mt Integrated Terminal

BUS-61559 SERIES MIL-STD-1553B NOTICE 2 ADVANCED INTEGRATED MUX HYBRIDS WITH ENHANCED RT FEATURES (AIM-HY’er) DESCRIPTION DDC’s BUS-61559 series of Advanced Integrated Mux Hybrids with enhanced RT Features (AIM-HY’er) comprise a complete interface between a microprocessor and a MIL-STD-1553B Notice 2 bus, implementing Bus Controller (BC), Remote Terminal (RX, and Monitor Terminal (MT) modes. Packaged in a single 78-pin DIP or 82-pin flat package the BUS-61559 series contains dual low-power transceivers and encoder/decoders, complete BC/RT/MT protocol logic, memory management and interrupt logic, 8K x 16 of shared static RAM, and a direct, buffered interface to a host processor bus. The BUS-61559 includes a number of advanced features in support of MIL-STD-1553B Notice 2 and STANAG 3838. Other salient features of the BUS-61559 serve to provide the benefits of reduced board space requirements enhanced software flexibility, and reduced host processor overhead buffers to provide a direct interface to a host processor bus. Alternatively, the buffers may be operated in a fully transparent mode in order to interface to up to 64K words of external shared RAM and/or connect directly to a component set supporting the 20 MHz STANAG-3910 bus. The memory management scheme for RT mode prevails an option for separation of broadcast data, in compliance with 1553B Notice 2. A circular buffer option for RT message data blocks offloads the host processor for bulk data transfer applications. Ano.


2006-01-02 : D8255AC    F10P40FR    F10P10Q    F10P09Q    F10P10F    F10P10R    F10P20F    F10P20FR    SE095N    SE005N   


@ 2014 :: Datasheetspdf.com ::
Semiconductors datasheet search & download site (Privacy Policy & Contact)