BR02

Core Logic %5[ ® $0,+*  PLFURQ &026 *DWH $UUD\ Description BR0x is a family of non-inverting bus receivers with a single output to be used as the output of tristate busses. Logic Symbol Truth Table BR0x AQ AQ AQ LL HH HDL Syntax Verilog .................... BR0x inst_name (Q, A); VHDL...................... inst_name: BR0x port map (Q, A); Pin Loading Pin Name A BR02 1.0 Equivalent Loads BR04 2.1 BR06 2.1 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) BR02 2.0 TBD 3.8 BR04 3.0 TBD 7.6 BR06 4.0 TBD 10.8 a. See page 2-15 for power equation. 3-41 %5[ $0,+*  PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process BR02 Number of Equivalent Loads From: Any Input To: Q tPLH tPHL Number of Equivalent Loads 1 0.22 0.23 1 8 0.32 0.35 14 BR04 From: Any Input To: Q tPLH tPHL 0.21 0.21 0.31 0.33 Number of Equivalent Loads 1 ...