AU11

Core Logic $8[ ® $0,+*  PLFURQ &026 *DWH $UUD\ Description AU1x is a family of combinational one-bit full adders. Logic Symbol AU1x CI CO A S B Truth Table CI A B S CO LLLLL L LHHL LHLHL L HH L H HL LHL HLHLH HHL LH HHHHH HDL Syntax Verilog .................... AU1x inst_name (CO, S, A, B, CI); VHDL...................... inst_name: AU1x port map (CO, S, A, B, CI); Pin Loading Pin Name A B CI Equivalent Loads AU11 AU12 4.2 8.6 4.2 8.5 3.2 6.5 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) AU11 7.0 TBD 12.5 AU12 15.0 TBD 26.5 a. See page 2-15 for power equation. 3-37 Core Logic $8[ ® $0,+*  PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Number of Equivalent Loads 1 4 AU11 From: A To: S tPLH tPHL From: B To: S tPLH tPHL From: Cl To: S tPLH tPHL From: A To: CO tPLH tPHL From: B To: CO tPLH tPHL From: CI To...