ATL25

Features Available in Gate Array or Embedded Array High-speed, 100 ps Gate Delay, 2-input NAND, FO = 2 (nominal) Up to 6.9 Million Used Gates and 976 Pins 0.25µ Geometry in up to Five-level Metal System-level Integration Technology www.datasheet4u.com – Cores: ARM7TDMI™, ARM920T™, ARM946E-S™ and MIPS64™ 5Kf™ RISC Microprocessors; AVR ® RISC Microcontroller; OakDSPCore™, Teak™ and PalmDSPCore™ Digital Signal Processors; 10/100 Ethernet MAC, USB, 1394, 1284, CAN and Other Assorted Processor Peripherals – Analog Functions: DACs, ADCs, OPAMPs, Comparators, PLLs and PORs – Soft Macro Memory: Gate Array SRAM — ROM — DPSRAM — FIFO – Hard Macro Memory: Embedded Array SRAM — ROM — DPSRAM — FIFO — Stacked E2 — Stacked Flash – I/O Interfaces: CMOS, LVTTL, LVDS, PCI, USB; Output Currents up to 16 mA @2.5V; 2.5V Native I/O, 3.3V Tolerant/Compliant I/O, 5.0V Tolerant I/O ASIC ATL25 Series Description The ATL25 Series ASIC family is fabricated on a 0.25µ CMOS process with up to five levels of metal. This family features arrays with up to 6.9 million routable gates and 976 pins. The high density and high pin count capabilities of the ATL25 family, coupled with the ability to add embedded microprocessor cores, DSP engines and memory on the same silicon, make the ATL25 series of ASICs an ideal choice for system-level integration. Figure 1. ATL25 Gate Array ASIC Standard Gate Array Architecture Figure 2. ATL25 Embedded Array ASIC Standard Gate Array Architecture Analog 1414C–A...