ASM5P23S05A

November 2004 www.DataSheet4U.com ASM5P23S09A ASM5P23S05A 3.3V ‘SpreadTrak’ Zero Delay Buffer rev 1.3 General Features 15 MHz to 133 MHz operating range, compatible with CPU and PCI bus frequencies. Zero input - output propagation delay. Multiple low-skew outputs. Output-output skew less than 250 pS. Device-device skew less than 700 pS. One input drives 9 outputs, grouped as 4+4+1 (ASM5P23S09A). One input drives 5 outputs (ASM5P23S05A). Less than 200 pS cycle-to-cycle jitter is compatible with Pentium based systems. Test Mode to bypass PLL (ASM5P23S09A only, refer Select Input Decoding Table). Available in 16-pin, 150-mil SOIC and 4.4 mm TSSOP packages for ASM5P23S09A and in 8-pin, 150-mil SOIC and 4.4 mm TSSOP packages for ASM5P23S05A. 3.3V operation Advanced 0.35< CMOS technology. ‘SpreadTrak’. ® out five low-skew clocks. The -1H version of the ASM5P23SxxA operates at up to 133 MHz frequency, and has higher drive than the -1 device. All parts have on-chip PLLs that lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The ASM5P23S09A has two banks of four outputs each, which can be controlled by the Select inputs as shown in the Select Input Decoding Table. If all the output clocks are not required, Bank B can be three-stated. The select input also allows the input clock to be directly applied to the outputs for chip and system testing purposes. Multiple ASM5P23S09A and ASM5P23S05A devices can accept the same input clock...