ASM5P2309A

September 2005 www.DataSheet4U.com ASM5P2309A ASM5P2305A 3.3V Zero Delay Buffer rev 1.6 General Features ƒ ƒ ƒ 15MHz to 133MHz operating range, compatible with CPU and PCI bus frequencies. Zero input - output propagation delay. Multiple low-skew outputs. ƒ ƒ ƒ ƒ ƒ ƒ ƒ Output-output skew less than 250pS. Device-device skew less than 700pS. One input drives 9 outputs, grouped as 4 + 4 + 1(ASM5P2309A). One input drives 5 outputs (ASM5P2305A). Less than 200 pS cycle-to-cycle jitter is compatible with Pentium® based systems. Test Mode to bypass PLL (ASM5P2309A only, Refer Select Input Decoding Table). Available in 16pin 150-mil SOIC, 4.4 mm TSSOP (ASM5P2309A), and in 8pin 150-mil SOIC package (ASM5P2305A). ƒ 3.3V operation, advanced 0.35µ CMOS technology. 133MHz frequencies, and has higher drive than the -1 devices. All parts have on-chip PLLs that lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The ASM5P2309A has two banks of four outputs each, which can be controlled by the Select inputs as shown in the Select Input Decoding Table. The select input also allows the input clock to be directly applied to the outputs for chip and system testing purposes. Multiple ASM5P2309A and ASM5P2305A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 700pS. All outputs have less than 200pS of cycle-to-cycle jitter. The input and output pr...