ASM5P2304B

September 2005 www.DataSheet4U.com rev 0.5 ASM5P2304B 3.3V Zero Delay Buffer Features ƒ ƒ ƒ ƒ Zero input - output propagation delay, adjustable by capacitive load on FBK input. Multiple configurations - Refer “ASM5P2304B Configurations Table”. Input frequency range: 4MHz to 20MHz Multiple low-skew outputs. ƒ ƒ ƒ ƒ ƒ ƒ ƒ Output-output skew less than 200pS. Device-device skew less than 500pS. Two banks of four outputs. has an on-chip PLL, which locks to an input clock, presented on the REF pin. The PLL feedback is required to be driven to FBK pin, and can be obtained from one of the outputs. The input-to-output propagation delay is guaranteed to be less than 250pS, and the output-to-output skew is guaranteed to be less than 200pS. The ASM5P2304B has two banks of two outputs each. Multiple ASM5P2304B devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 500pS. The ASM5P2304B is available in two different Less than 200pS Cycle-to-Cycle jitter (-1, -1H, -2, -2H). Available in space saving, 8-pin 150 mil SOIC Package. 3.3V operation. Advanced 0.35µ CMOS technology. Industrial temperature available. configurations (Refer “ASM5P2304B Configurations Table). The ASM5P2304B-1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The ASM5P2304B-1H is the high-drive version of the -1 and the rise and fall times on this device are mu...