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ASM5I9352 Datasheet

Part Number ASM5I9352
Manufacturers Alliance Semiconductor
Logo Alliance Semiconductor
Description 11-Output Zero Delay Buffer
Datasheet ASM5I9352 DatasheetASM5I9352 Datasheet (PDF)

July 2005 rev 0.2 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer Features ƒ ƒ ƒ Output frequency range: 25MHz to 200MHz Output frequency range: 16.67MHz to 200MHz Input frequency range: 16.67MHz to 200MHz ASM5I9352 The ASM5I9352 features an LVCMOS reference clock input and provides 11 outputs partitioned in 3 banks of 5, 4, and 2 outputs. Bank A divides the VCO output by 4 or 6 while Bank B divides by 4 and 2 and Bank C divides by 2 and 4 per SEL(A:C) settings, see Table 2. These dividers .

  ASM5I9352   ASM5I9352






Part Number ASM5I9351
Manufacturers Alliance Semiconductor
Logo Alliance Semiconductor
Description 9-Output Zero Delay Buffer
Datasheet ASM5I9352 DatasheetASM5I9351 Datasheet (PDF)

July 2005 rev 0.2 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer Features ƒ ƒ ƒ Output frequency range: 25 MHz to 200 MHz Input frequency range: 25 MHz to 200 MHz 2.5V or 3.3V operation ASM5I9351 The ASM5I9351 features LVPECL and LVCMOS reference clock inputs and provides 9 outputs partitioned in 4 banks of 1, 1, 2, and 5 outputs. Bank A divides the VCO output by 2 or 4 while the other banks divide by 4 or 8 per SEL(A:D) settings, see Table.2. These dividers allow output to input ratios of .

  ASM5I9352   ASM5I9352







Part Number ASM5I9350
Manufacturers Alliance Semiconductor
Logo Alliance Semiconductor
Description 3.3V 1:10 LVCMOS PLL Clock Generator
Datasheet ASM5I9352 DatasheetASM5I9350 Datasheet (PDF)

July 2005 rev 0.2 3.3V 1:10 LVCMOS PLL Clock Generator Features ƒ ƒ ƒ Output frequency range: 25 MHz to 200 MHz Input frequency range: 6.25 MHz to 31.25 MHz 2.5V or 3.3V operation ASM5I9350 The ASM5I9350 features Xtal and LVCMOS reference clock inputs and provides nine outputs partitioned in four banks of 1, 1, 2, and 5 outputs. Bank A divides the VCO output by 2 or 4 while the other banks divide by 4 or 8 per SEL(A:D) settings, see Table 2. These dividers allow output to input ratios of 16:1,.

  ASM5I9352   ASM5I9352







11-Output Zero Delay Buffer

July 2005 rev 0.2 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer Features ƒ ƒ ƒ Output frequency range: 25MHz to 200MHz Output frequency range: 16.67MHz to 200MHz Input frequency range: 16.67MHz to 200MHz ASM5I9352 The ASM5I9352 features an LVCMOS reference clock input and provides 11 outputs partitioned in 3 banks of 5, 4, and 2 outputs. Bank A divides the VCO output by 4 or 6 while Bank B divides by 4 and 2 and Bank C divides by 2 and 4 per SEL(A:C) settings, see Table 2. These dividers allow output to input ratios of 3:1, 2:1, 3:2, 1:1, 2:3, 1:2, and 1:3. Each LVCMOS compatible output can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:22. ƒ 2.5V or 3.3V operation www.DataSheet4U.com ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ Split 2.5V/3.3V outputs ± 2% max Output duty cycle variation 11 Clock outputs: Drive up to 22 clock lines LVCMOS reference clock input 125-pS max output-output skew PLL bypass mode Spread Aware TM The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 16.67 MHz to 200 MHz. For normal operation, the external feedback input, FB_IN, is connected to one of the outputs. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see Table 1. Output enable/disable Pin compatible with MPC9352 and MPC952 Indu.


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