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ASM5I9350

Alliance Semiconductor
Part Number ASM5I9350
Manufacturer Alliance Semiconductor
Description 3.3V 1:10 LVCMOS PLL Clock Generator
Published May 9, 2008
Detailed Description July 2005 rev 0.2 3.3V 1:10 LVCMOS PLL Clock Generator Features ƒ ƒ ƒ Output frequency range: 25 MHz to 200 MHz Input fr...
Datasheet PDF File ASM5I9350 PDF File

ASM5I9350
ASM5I9350

Overview
July 2005 rev 0.
2 3.
3V 1:10 LVCMOS PLL Clock Generator Features ƒ ƒ ƒ Output frequency range: 25 MHz to 200 MHz Input frequency range: 6.
25 MHz to 31.
25 MHz 2.
5V or 3.
3V operation ASM5I9350 The ASM5I9350 features Xtal and LVCMOS reference clock inputs and provides nine outputs partitioned in four banks of 1, 1, 2, and 5 outputs.
Bank A divides the VCO output by 2 or 4 while the other banks divide by 4 or 8 per SEL(A:D) settings, see Table 2.
These dividers allow output to input ratios of 16:1, 8:1, 4:1, and 2:1.
Each LVCMOS compatible output can drive 50Ω series or parallel terminated transmission lines.
For series terminated transmission lines, each output can drive one or two traces givi...


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