AS7C33512NTF32A

April 2005 ® AS7C33512NTF32A AS7C33512NTF36A 3.3V 512K × 32/36 Flowthrough Synchronous SRAM with NTDTM Features Organization: 524,288 words × 32 or 36 bits NTD™architecture for efficient bus operation Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous operation Flow-through mode Asynchronous output enable control Available in 100-pin TQFP package www.DataSheet4U.com Individual byte write and global write Clock enable for operation hold Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Self-timed write cycles Interleaved or linear burst modes Snooze mode for standby operation Logic block diagram A[18:0] 19 D Address register Burst logic Q 19 CLK CE0 CE1 CE2 R/W BWa BWb BWc BWd ADV / LD LBO ZZ D Q 19 Write delay addr. registers CLK Control logic CLK Write Buffer CLK 512K x 32/36 SRAM Array DQ[a,b,c,d] 32/36 D Data Q Input Register CLK 32/36 32/36 32/36 32/36 CLK CEN OE Output Buffer 32/36 OE DQ[a,b,c,d] Selection guide -75 Minimum cycle time Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 8.5 7.5 275 90 60 -85 10 8.5 250 80 60 -10 12 10 230 80 60 Units ns ns mA mA mA 4/21/05, v 1.3 Alliance Semiconductor P. 1 of 18 Copyright © Alliance Semiconductor. All rights reserved. AS7C33512NTF32A/36A ® 16 Mb Synchronous SRAM products list1,2 Org 1MX18 512KX32 512KX3...