February 2005
®
AS7C332MPFD18A
3.3V 2M × 18 pipelined burst synchronous SRAM
Features
• Organization: 2,097,152 words ...
February 2005
®
AS7C332MPFD18A
3.3V 2M × 18 pipelined burst synchronous SRAM
Features
Organization: 2,097,152 words × 18 bits Fast clock speeds to 200 MHz Fast clock to data access: 3.1/3.5/3.8 ns Fast OE access time: 3.1/3.5/3.8 ns Fully synchronous register-to-register operation Double-cycle deselect Asynchronous output enable control Available in 100-pin TQFP package www.DataSheet4U.com Individual byte write and global write Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs
Logic block diagram
LBO
CLK ADV ADSC ADSP A[20:0] CLK CS CLR
Burst logic
Q
21
CS Address register CLK
D
21
19 21
2M x 18 Memory array 18 18
GWE BWb BWE BWa CE0 CE1 CE2
D DQb
Q
CLK D DQa Q
Byte Write registers
Byte Write
CLK D
registers
2
OE
Enable Q register
CE CLK ZZ
Output registers
CLK
Input registers
CLK
Power down
D Enable Q
delay register
CLK OE
18
DQ[a,b]
Selection guide
Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum
CMOS standby current (DC) -200 5 200 3.1 450 170 90 -166 6 166 3.5 400 150 90 -133 7.5 133 3.8 350 140 90 Units ns MHz ns mA mA mA
2/10/05, v.1.1
Alliance Semiconductor
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AS7C332MPFD18A
®
32 Mb Synchronous SRAM pro...
