AS7C332MNTF18A

December 2004 ® AS7C332MNTF18A 3.3V 2M x 18 Flowthrough SRAM with NTDTM Features Organization: 2,097,152 words × 18 bits NTD™architecture for efficient bus operation Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous operation Flow-through mode Asynchronous output enable control Available in 100-pin TQFP package Byte write enables Clock enable for operation hold Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Self-timed write cycles Interleaved or linear burst modes Snooze mode for standby operation www.DataSheet4U.com Logic block diagram A[19:0] 20 D Address register burst logic Q 20 CLK CE0 CE1 CE2 R/W BWa BWb ADV / LD LBO ZZ CLK D Q 20 Write delay addr. registers CLK Control logic CLK Write Buffer 2M x 18 SRAM array DQ [a,b] 18 D Data Q input register CLK 18 18 18 18 CLK CEN OE Output buffer 18 OE DQ [a,b] Selection guide -75 Minimum cycle time Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 8.5 7.5 325 140 90 -85 10 8.5 300 130 90 -10 12 10 375 130 90 Units ns ns mA mA mA 12/23/04, v 1.2 Alliance Semiconductor P. 1 of 18 Copyright © Alliance Semiconductor. All rights reserved. AS7C332MNTF18A ® 32 Mb Synchronous SRAM products list1,2 Org 2MX18 1MX32 1MX36 2MX18 1MX32 1MX36 2MX18 1MX32 www.DataSheet4U.com 1MX36 2MX18 1MX32 1MX36 2MX18 1MX32 1MX36 Part ...