AS7C33256PFS16A

March 2001 ® AS7C33256PFS16A AS7C33256PFS18A 3.3V 256K × 16/18 pipeline burst synchronous SRAM Features Organization: 262,144 words × 16 or 18 bits Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access: 3.5/3.8/4.0/5.0 ns Fast OE access time: 3.5/3.8/4.0/5.0 ns Fully synchronous register-to-register operation “Flow-through” mode Single-cycle deselect - Dual-cycle deselect also available (AS7C33256PFD16A/ www.DataSheet4U.com AS7C33256PFD18A) Pentium®* compatible architecture and timing Asynchronous output enable control Economical 100-pin TQFP package Byte write enables Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ 30 mW typical standby power in power down mode NTD™* pipeline architecture available (AS7C33256NTD16A/AS7C33256NTD18A) Logic block diagram LBO CLK ADV ADSC ADSP A[17:0] CLK CS CLR Pin arrangement 256K × 16/18 Memory array 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 Burst logic Q A6 A7 CE0 CE1 NC NC BWb BWa CE2 VDD VSS CLK GWE BWE OE ADSC ADSP ADV A8 A9 18 D CS CLK 18 16 18 Address register NC NC NC VDDQ VSSQ NC NC DQb DQb VSSQ VDDQ DQb DQb FT VDD NC VSS DQb DQb VDDQ VSSQ DQb DQb DQpb/NC NC VSSQ VDDQ NC NC NC 16/18 16/18 GWE BWb BWE BWa CE0 CE1 CE2 D DQb Q Byte Write registers Byte Write registers CLK D CLK D DQa Q 2 OE Enable Q register Enable Q delay register CE CLK Output registers CLK Input registers CLK ZZ Power ...