AS7C33256NTD36A

November 2004 ® AS7C33256NTD32A AS7C33256NTD36A 3.3V 256K×32/36 Pipelined burst Synchronous SRAM with NTDTM Features Organization: 262,144 words × 32 or 36 bits NTD™architecture for efficient bus operation Fast clock speeds to 166 MHz Fast clock to data access: 3.5/4.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous operation Common data inputs and data outputs www.DataSheet4U.com Asynchronous output enable control Available in 100-pin TQFP Byte write enables Clock enable for operation hold Multiple chip enables for easy expansion 3.3 core power supply 2.5V or 3.3V I/O operation with separate VDDQ Self-timed write cycles Interleaved or linear burst modes Snooze mode for standby operation Logic Block Diagram A[17:0] 18 D Address register Burst logic Q 18 CLK D CE0 CE1 CE2 R/W BWa BWb BWc BWd ADV / LD LBO ZZ 36/32 Write delay addr. registers CLK Q 18 Control logic CLK Write Buffer CLK 36/32 256K x 32/36 SRAM Array DQ [a:d] D Data Q Input Register CLK 36/32 36/32 36/32 CLK CEN CLK Output Register OE 36/32 OE DQ[a:d] Selection Guide -166 Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 6 166 3.5 475 130 30 -133 7.5 133 4 400 100 30 Units ns MHz ns mA mA mA 11/30/04, v. 2.1 Alliance Semiconductor P. 1 of 19 Copyright © Alliance Semiconductor. All rights reserved. AS7C33256NTD32A AS7C33256NTD36A ® 8 Mb Synchronou...