AS7C331MNTD18A

December 2004 ® AS7C331MNTD18A 3.3V 1M x 18 Pipelined SRAM with NTDTM Features Organization: 1,048,576 words × 18 bits NTD™ architecture for efficient bus operation Fast clock speeds to 166 MHz Fast clock to data access: 3.4/3.8 ns Fast OE access time: 3.4/3.8 ns Fully synchronous operation Asynchronous output enable control Available in 100-pin TQFP package Individual byte write and global write Clock enable for operation hold Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Self-timed write cycles Interleaved or linear burst modes Snooze mode for standby operation www.DataSheet4U.com Logic block diagram A[19:0] 20 D Address register burst logic Q 20 CLK CE0 CE1 CE2 R/W BWa BWb ADV / LD LBO ZZ 18 CLK D Q 20 Write delay addr. registers CLK Control logic CLK Write Buffer 1M x 18 SRAM array DQ [a,b] D Data Q input register CLK 18 18 18 18 CLK CEN CLK OE Output register 18 OE DQ [a,b] Selection guide -166 Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 6 166 3.4 290 90 60 -133 7.5 133 3.8 270 80 60 Units ns MHz ns mA mA mA 12/24/04, v 2.7 Alliance Semiconductor P. 1 of 18 Copyright © Alliance Semiconductor. All rights reserved. AS7C331MNTD18A ® 16 Mb Synchronous SRAM products list1,2 Org 1MX18 512KX32 512KX36 1MX18 512KX32 512KX36 1MX18 512KX32 www.DataShe...