AS7C33128NTD32B

February 2005 ® AS7C33128NTD32B AS7C33128NTD36B 3.3V 128K×32/36 Pipelined SRAM with NTDTM Features Organization: 131,072 words × 32 or 36 bits NTD™ architecture for efficient bus operation Fast clock speeds to 200 MHz Fast clock to data access: 3.0/3.5/4.0 ns Fast OE access time: 3.0/3.5/4.0 ns Fully synchronous operation Asynchronous output enable control Available in 100-pin TQFP package www.DataSheet4U.com Byte write enables Clock enable for operation hold Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Self-timed write cycles Interleaved or linear burst modes Snooze mode for reduced power standby Logic block diagram A[16:0] 17 D Burst logic CE0 CE1 CE2 Address register Q 17 17 D 17 Q CLK Write delay addr. registers CLK 17 R/W BWa BWb BWc BWd ADV / LD LBO ZZ Control logic Write Data Registers CLK CLK 128K x 32/36 SRAM Array DQ [a:d] 32/36 D Data Q Input Register CLK 32/36 32/36 32/36 32/36 CLK CEN CLK OE Output Register 32/36 OE DQ [a:d] Selection Guide -200 Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 5 200 3.0 375 135 30 -166 6 166 3.5 350 120 30 -133 7.5 133 4 325 110 30 Units ns MHz ns mA mA mA 2/8/05; v.1.5 Alliance Semiconductor P. 1 of 18 Copyright © Alliance Semiconductor. All rights reserved. AS7C33128NTD32B AS7C33128NTD36B ® 4 Mb ...