April 2005
®
AS7C33128NTD18B
3.3V 128K×18 Pipelined SRAM with NTDTM
Features • Organization: 131,072 words × 18 bits •...
April 2005
®
AS7C33128NTD18B
3.3V 128K×18 Pipelined SRAM with NTDTM
Features Organization: 131,072 words × 18 bits NTD™ architecture for efficient bus operation Fast clock speeds to 200 MHz Fast clock to data access: 3.0/3.5/4.0 ns Fast OE access time: 3.0/3.5/4.0 ns Fully synchronous operation Asynchronous output enable control Available in 100-pin TQFP package www.DataSheet4U.com Byte write enables Clock enable for operation hold Logic block diagram
A[16:0] 17
D
Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Self-timed write cycles Interleaved or linear burst modes Snooze mode for standby operation
Address register Burst logic
Q
17 17 Write delay addr. registers
CLK D Q
CLK
CE0 CE1 CE2 R/W BWa BWb ADV / LD LBO ZZ DQ [a:b] 18
17
Control logic
CLK
CLK
Write Buffer
128K x 18 SRAM Array
D
Data Q Input Register
CLK
18
18
18
18 CLK CEN
CLK OE
Output Register 18
OE
DQ [a:b]
Selection Guide
-200 Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum
CMOS standby current (DC) 5 200 3.0 375 135 30 -166
6 166 3.5 350 120
-133
7.5 133 4 325 110
Units ns MHz ns mA mA mA
30
30
4/28/05; v.1.3
Alliance Semiconductor
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AS7C33128NTD18B
®
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