ADL5391

www.DataSheet4U.com DC to 2.0 GHz Multiplier ADL5391 FEATURES Ultrafast symmetric multiplier Function: VW = α × (VX × VY)/1 V + VZ Unique design ensures absolute XY-symmetry Identical X and Y amplitude/timing responses Adjustable gain scaling, α DC-coupled throughout, 3 dB bandwidth of 2 GHz Fully differential inputs, may be used single ended Low noise, high linearity Accurate, temperature stable gain scaling Single-supply operation (4.5 V to 5.5 V @ 130 mA) Low current power-down mode 16-lead LFCSP FUNCTIONAL BLOCK DIAGRAM YMNS YPLS GADJ XPLS XMNS ZMNS ZPLS WPLS ENBL VMID WMNS ADL5391 COMM VPOS 06059-001 W = αXY/1V+Z Figure 1. APPLICATIONS Wideband multiplication and summing High frequency analog modulation Adaptive antennas (diversity/phased array) Square-law detectors and true rms detectors Accurate polynomial function synthesis DC capable VGA with very fast control GENERAL DESCRIPTION The ADL5391 draws on three decades of experience in advanced analog multiplier products. It provides the same general mathematical function that has been field proven to provide an exceptional degree of versatility in function synthesis. VW = α × (VX × VY)/ 1 V + VZ The most significant advance in the ADL5391 is the use of a new multiplier core architecture, which differs markedly from the conventional form that has been in use since 1970. The conventional structure that employs a current mode, translinear core is fundamentally asymmetric with respect to the X and Y inputs, leadin...