ADC08DL500

ADC08DL500 www.ti.com SNAS495C – MARCH 2011 – REVISED MARCH 2011 ADC08DL500 Low Power, 8-Bit, Dual 500 MSPS A/D Converter Check for Samples: ADC08DL500 FEATURES 1 2 Single +1.9V ±0.1V Operation Duty Cycle Corrected Sample Clock APPLICATIONS Satellite Modems Digital Oscilloscopes Direct RF Down Conversion Communications Systems Test Instrumentation DESCRIPTION The ADC08DL500 is a dual, low power, high performance, CMOS analog-to-digital converter. The ADC08DL500 digitizes signals to 8 bits of resolution at sample rates up to 500 MSPS. Consuming a typical 1.2 Watts in demultiplex mode at 500 MSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the calibration schemes enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.2 Effective Number of Bits (ENOB) with a 125 MHz input signal and a 500 MHz sample rate while providing a 10−18 Code Error Rate (C.E.R.) The converter typically consumes 3.3 mW in the Power Down Mode and is available in a lead-free 144-lead LQFP and operates over the modified Industrial (-40°C ≤ TA ≤ +70°C) temperature range. Resolution Max Conversion Rate Code Error Rate ENOB @ 125 MHz Input DNL Power Consumption Table 1. Key Specifications Operating in 1:2 Demux Output Po...