AD9251

Data Sheet 14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9251 07938-001 FEATURES 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR 74.3 dBFS at 9.7 MHz input 71.5 dBFS at 200 MHz input SFDR 93 dBc at 9.7 MHz input 80 dBc at 200 MHz input Low power 33 mW per channel at 20 MSPS 73 mW per channel at 80 MSPS Differential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = ±0.45 LSB Serial port control options Offset binary, gray code, or twos complement data format Optional clock duty cycle stabilizer Integer 1-to-8 input clock divider Data output multiplex option Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock out with programmable clock and data alignment APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Battery-powered instruments Hand held scope meters Portable medical imaging Ultrasound Radar/LIDAR FUNCTIONAL BLOCK DIAGRAM AVDD GND SDIO SCLK CSB VIN+A VIN–A VREF SENSE VCM RBIAS VIN–B VIN+B REF SELECT SPI ADC PROGRAMMING DATA MUX OPTION AD9251 ADC DIVIDE DUTY CYCLE 1 TO 8 STABILIZER MODE CONTROLS CMOS OUTPUT BUFFER CMOS OUTPUT BUFFER ORA D13A D0A DCOA DRVDD ORB D13B D0B DCOB CLK+ CLK– SYNC DCS Figure 1. PDWN DFS OEB PRODUCT HIGHLIGHTS 1. The AD9251 operates from...