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GSM/GPRS Digital Baseband Processor For Smartphone and Wireless Handheld Devices
Preliminary Techn...
www.DataSheet4U.com
GSM/GPRS Digital Baseband Processor For Smartphone and Wireless Handheld Devices
Preliminary Technical Data
FEATURES
Complete Single Chip Programmable Digital Baseband Processor divided into three main subsystems: Control Processor Subsystem including: ® 32-bit MCU ARM7TDMI Control Processor On-chip System SRAM Memory DSP Subsystem including 16-bit Fixed Point DSP Processor Expanded Data and Program SRAM Program Instruction Cache Full Rate, Enhanced Full Rate and Half Rate Speech Encoding/Decoding DMA Subsystem including 16/32 channel chaining DMA Peripheral Functions Parallel and Serial Display Interface Fast USB slave interface/ Fast IrDA SPI slave/master MMC/SD-Card support Keypad Interface FLASH Memory Interface Pseudo SRAM support 13/26 MHz clock detection 1.8V and 3.0V, 64 kbps SIM Interface Universal System Connector Interface Baseband Converter Interface Data Services Interface Control of Radio Subsystem Three independent programmable backlight outputs Real Time Clock with Alarm Programmable Power and Clock Management Slow Clocking Scheme for Low Idle Mode Current Power Down modes On-chip support for GSM Data Services up to 14.4kbits/sec, Class 12 GPRS, HSCSD JTAG Interface for Test and In-Circuit Emulation 1.8V Typical Operating
Voltage Operating
Voltage Range 1.7V - 1.9V Independent I/O and Memory
Voltages 160-Ball LFBGA (mini-BGA) package
AD6528
UNIVERSAL SYSTEM CONN. INTERFACE
DSP
CHANNEL CODEC CHANNEL EQUALIZER SPEECH CODEC
VOICEBAND / B...