512Mb DDRII Synchronous DRAM
A3R12E30CBF A3R12E40CBF
512Mb DDRII Synchronous DRAM
512Mb DDRII SDRAM Specification
A3R12E30CBF A3R12E40CBF
Zentel Ele...
Description
A3R12E30CBF A3R12E40CBF
512Mb DDRII Synchronous DRAM
512Mb DDRII SDRAM Specification
A3R12E30CBF A3R12E40CBF
Zentel Electronics Corp.
Revision 1.2
Sep., 2013
A3R12E30CBF A3R12E40CBF
512Mb DDRII Synchronous DRAM
Specifications
Density: 512M bits Organization ⎯ 16M words × 8 bits × 4 banks (A3R12E30CBF) ⎯ 8M words × 16 bits × 4 banks (A3R12E40CBF) Package ⎯ 60-ball FBGA(μBGA) (A3R12E30CBF) ⎯ 84-ball FBGA(μBGA) (A3R12E40CBF) ⎯ Lead-free (RoHS compliant) Power supply: VDD, VDDQ = 1.8V ± 0.1V Data rate: 1066Mbps/800Mbps(max.) 1KB page size (A3R12E30CBF) ⎯ Row address: A0 to A13 ⎯ Column address: A0 to A9 2KB page size (A3R12E40CBF) ⎯ Row address: A0 to A12 ⎯ Column address: A0 to A9 Four internal banks for concurrent operation Interface: SSTL_18 Burst lengths (BL): 4, 8 Burst type (BT): ⎯ Sequential (4, 8) ⎯ Interleave (4, 8) /CAS Latency (CL): 3, 4, 5, 6, 7 Precharge: auto precharge option for each burst
access Driver strength: normal/weak Refresh: auto-refresh, self-refresh Refresh cycles: 8192 cycles/64ms ⎯ Average refresh period
7.8μs at 0°C ≤ TC ≤ +85°C 3.9μs at +85°C < TC ≤ +95°C Operating case temperature range ⎯ TC = 0°C to +95°C
Features
Double-data-rate architecture; two data transfers per clock cycle
The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
DQS is edge-ali...
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