8F32256C

EDI8F32256C 256Kx32 SRAM Module Features 256Kx32 bit CMOS Static Random Access Memory Access Times BiCMOS: 10 and 12ns CMOS: 15, 20, 25, and 35ns Individual Byte Selects Fully Static, No Clocks TTL Compatible I/O High Density Package with JEDEC Standard Pinouts 64 Pin ZIP, No. 85 64 Lead Angled SIMM, No. 32 64 Lead SIMM, No. 333 64 ZIP Low Profile, No. 188 Common Data Inputs and Outputs Single +5V (±10%) Supply Operation 256Kx32 Static RAM CMOS, High Speed Module The EDI8F32256C is a high speed 8 megabit Static RAM module organized as 256K words by 32 bits. This module is constructed from eight 256Kx4 Static RAMs in SOJ packages on an epoxy laminate (FR4) board. Four chip enables (EØ-E3) are used to independently enable the four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. The EDI8F32256C is offered in 64 pin ZIP/SIMM package which enables eight megabits of memory to be placed in less than 1.4 square inches of board space. All inputs and outputs are TTL compatible and operate from a single 5V supply. Fully asynchronous circuitry requires no clocks or refreshing for operation and provides equal access and cycle times for ease of use. The ZIP and SIMM modules contain two pins, PD1 and PD2, which are used to identify module memory density in applications where alternate modules can be interchanged. www.DataSheet4U.com Pin Configurations and Block Diagram PD1 DQØ DQ1 DQ2 DQ3...