Communications Processor
IDTTM InterpriseTM Integrated Communications Processor
79RC32355
Features List
◆ RC32300 32-bit Microprocessor – Enhan...
Description
IDTTM InterpriseTM Integrated Communications Processor
79RC32355
Features List
◆ RC32300 32-bit Microprocessor – Enhanced MIPS-II ISA – Enhanced MIPS-IV cache prefetch instruction – DSP Instructions – MMU with 16-entry TLB – 8KB Instruction Cache, 2-way set associative – 2KB Data Cache, 2-way set associative – Per line cache locking – Write-through and write-back cache management – Debug interface through the EJTAG port – Big or Little endian support
◆ Interrupt Controller – Allows status of each interrupt to be read and masked
◆ I2C – Flexible I2C standard serial interface to connect to a variety of peripherals – Standard and fast mode timing support – Configurable 7 or 10-bit addressable slave
◆ UARTs – Two 16550 Compatible UARTs – Baud rate support up to 1.5 Mb/s
◆ Counter/Timers – Three general purpose 32-bit counter/timers
◆ General Purpose I/O Pins (GPIOP) – 36 individually programmable pins – Each pin programmable as input, output, or alternate function – Input can be an interrupt or NMI source – Input can also be active high or active low
Block Diagram
◆ SDRAM Controller
– 2 memory banks, non-interleaved, 512 MB total – 32-bit wide data path – Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips – SODIMM support – Stays on page between transfers – Automatic refresh generation ◆ Peripheral Device Controller
– 26-bit address bus – 32-bit data bus with variable width support of 8-,16-, or 32-bits – 8-bit boot ROM support – 6 banks available, up to 64MB per bank – Suppor...
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