74SSTUB32865

74SSTUB32865 www.ti.com SLAS537 – NOVEMBER 2007 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 2 Member of the Texas Instruments Widebus+™ Family Pinout Optimizes DDR2 RDIMM PCB Layout 1-to-2 Outputs Supports Stacked DDR2 RDIMMs Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line Supports SSTL_18 Data Inputs Differential Clock (CK and CK) Inputs Supports LVCMOS Switching Levels on the Chip-Select Gate-Enable and RESET Inputs Checks Parity on DIMM-Independent Data Inputs Industrial Temperature range for TA -40°C to 85°C supported RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low, Except PTYERR DESCRIPTION This 28-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. One device per DIMM is required to drive up to 18 SDRAM loads or two devices per DIMM are required to drive up to 36 SDRAM loads. All inputs are SSTL_18, except the chip-select gate-enable (CSGateEN) and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specifications, except the open-drain error (PTYERR) output. The 74SSTUB32865 operates from a differential clock (CK and CK). Data are registered at the crossing of CK going high and CK going low. The 74SSTUB32865 accepts a p...