74LV03

INTEGRATED CIRCUITS 74LV03 Quad 2-input NAND gate Product specification Supersedes data of 1997 Mar 28 IC24 Data Handbook 1998 Apr 20 Philips Semiconductors Philips Semiconductors Product specification Quad 2-input NAND gate 74LV03 FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for Low Voltage applications: 1.0 to 3.6V Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V Typical VOLP (output ground bounce) t 0.8V @ VCC = 3.3V, Typical VOHV (output VOH undershoot) u 2V @ VCC = 3.3V, Level shifter capability Output capability: standard ICC category: SSI Tamb = 25°C Tamb = 25°C DESCRIPTION The 74LV03 is a low–voltage Si–gate CMOS device and is pin and function compatible with 74HC/HCT03. The 74LV03 provides the 2–input NAND function. The 74LV03 has open–drain N–transistor outputs, which are not clamped by a diode connected to VCC. In the OFF–state, i.e. when one input is LOW, the output may be pulled to any voltage between GND and VOmax. This allows the device to be used as a LOW–to–HIGH or HIGH–to–LOW level shifter. For digital operation and OR–tied output applications, these devices must have a pull–up resistor to establish a logic HIGH level. (open drain) QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr =tf v2.5 ns SYMBOL tPZL/tPLZ CI CPD PARAMETER Propagation delay nA, nB to nY Input capacitance Power dissipation capacitance per gate Notes 1, 2 CONDITIONS CL = 15pF VCC = 3.3V TYPICAL 8 3.5 4 UNIT ns pF pF NOTES: 1 CPD is used to determ...