DatasheetsPDF.com

74LS90 Datasheet

Part Number 74LS90
Manufacturers ETC
Logo ETC
Description DECADE COUNTER
Datasheet 74LS90 Datasheet74LS90 Datasheet (PDF)

54/7490A 54LS/74LS90 DECADE COUNTER 90 CONNECTION DIAGRAM PINOUT A DESCRIPTION — The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby-five counter. It can be connected to operate with a conventional BCD out­ put pattern or it can be connected to provide a 50% duty cycle output. In the BCD mode, HIGH signals on the Master Set (MS) inputs set the outputs to BCD nine. HIGH signals on the Master Reset (MR) inpu.

  74LS90   74LS90






Part Number 74LS90
Manufacturers Texas Instruments
Logo Texas Instruments
Description DIVIDE-BY-TWELVE AND BINARY COUNTERS
Datasheet 74LS90 Datasheet74LS90 Datasheet (PDF)

SN5490A, SN5492A, SN5493A, SN54LS90, SN54LS92, SN54LS93 SN7490A, SN7492A, SN7493A, SN74LS90, SN74LS92, SN74LS93 DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS SDLS940A – MARCH 1974 – REVISED MARCH 1988 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright © 1988, Texas.

  74LS90   74LS90







Part Number 74LS90
Manufacturers National Semiconductor
Logo National Semiconductor
Description Decade and Binary Counters
Datasheet 74LS90 Datasheet74LS90 Datasheet (PDF)

DM74LS90 DM74LS93 Decade and Binary Counters June 1989 DM74LS90 DM74LS93 Decade and Binary Counters General Description Each of these monolithic counters contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for which the count cycle length is divide-by-five for the ’LS90 and divideby-eight for the ’LS93 All of these counters have a gated zero reset and the LS90 also has gated set-to-nine inputs for use in BCD nine’s compl.

  74LS90   74LS90







Part Number 74LS90
Manufacturers Motorola
Logo Motorola
Description DECADE COUNTER
Datasheet 74LS90 Datasheet74LS90 Datasheet (PDF)

DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are high-speed 4-bit ripple type counters partitioned into two sections. Each counter has a divide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transition on the clock inputs. Each section can be used separately or tied together (Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 .

  74LS90   74LS90







Part Number 74LS90
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description Decade and Binary Counters
Datasheet 74LS90 Datasheet74LS90 Datasheet (PDF)

DM74LS90 Decade and Binary Counters August 1986 Revised March 2000 DM74LS90 Decade and Binary Counters General Description Each of these monolithic counters contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for which the count cycle length is divide-by-five for the DM74LS90. All of these counters have a gated zero reset and the DM74LS90 also has gated set-to-nine inputs for use in BCD nine’s complement applications. To.

  74LS90   74LS90







DECADE COUNTER

54/7490A 54LS/74LS90 DECADE COUNTER 90 CONNECTION DIAGRAM PINOUT A DESCRIPTION — The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby-five counter. It can be connected to operate with a conventional BCD out­ put pattern or it can be connected to provide a 50% duty cycle output. In the BCD mode, HIGH signals on the Master Set (MS) inputs set the outputs to BCD nine. HIGH signals on the Master Reset (MR) inputs force all outputs LOW. For a similar counter with corner power pins, see the ’LS290; for dual versions, see the ’LS390 and ’LS490. ORDERING CODE: See Section 9 PKGS PIN OUT COMMERCIAL GRADE Vcc = +5.0 V ±5%, T a = 0°C to +70°C MILITARY GRADE Vcc = +5.0 V ±10%, TA = -55° C to +125° C Plastic DIP (P) A 7490APC, 74LS90PC Ceramic DIP (D) A 7490ADC, 74LS90DC 5490ADM, 54LS90DM Flatpak (F) A 7490AFC, 74LS90FC 5490AFM, 54LS90FM PKG TYPE 9A 6A 3I LOGIC SYMBOL 67 Vcc = Pin 5 GND = Pin 10 NC = Pins 4,13 INPUT LOADING/FAN-OUT: See Section 3 for U.L. defintions PIN NAMES DESCRIPTION CPo CPi MRi, MR2 MSi , MS2 Qo +2 Section Clock Input (Active Falling Edge) -H5 Section Clock Input (Active Falling Edge) Asynchronous Master Reset Inputs (Active HIGH) Asynchronous Master Set (Preset 9) Inputs (Active HIGH) -j-2 Section Output* -^-5 Section Outputs *The Qo output is guaranteed to drive the full rated fan-out plus the C P i input. 54/74 (U.L.) HIGH/LOW 2.0/2.0 3.0/3.0 1.0/1.0 1.0.


2019-10-23 : TPS75301-EP    TPS75315-EP    TPS75333-EP    TPS75325-EP    TPS75101Q    TPS75115Q    TPS75118Q    TPS75325-Q1    TPS75333-Q1    TPS75101-EP   


@ 2014 :: Datasheetspdf.com ::
Semiconductors datasheet search & download site (Privacy Policy & Contact)