74HCT7597

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT7597 8-bit shift register with input latches Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 8-bit shift register with input latches FEATURES 8-bit parallel input latches Shift register has direct overriding load and clear Output capability: standard ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT7597 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. 74HC/HCT7597 The 74HC/HCT7597 both consist of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit shift register. When LE is LOW, data at the Dn inputs enter the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes. When LE is HIGH the latches store the information that was present at the D-inputs, a set-up time preceding the LOW-to-HIGH transition of LE. The shift register has a positive edge-triggered clock, direct load (from storage) and clear inputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay SHCP to Q LE to Q PL to Q D7 ...