74HCT4518

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4518 Dual synchronous BCD counter Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Dual synchronous BCD counter Product specification 74HC/HCT4518 FEATURES Output capability: standard ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4518 are high-speed Si-gate CMOS devices and are pin compatible with the “4518” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4518 are dual 4-bit internally synchronous BCD counters with an active HIGH clock input (nCP0) and an active LOW clock input (nCP1), buffered outputs from all four bit positions (nQ0 to nQ3) and an active HIGH overriding asynchronous master reset input (nMR). The counter advances on either the LOW-to-HIGH transition of nCP0 if nCP1 is HIGH or the HIGH-to-LOW transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on nMR resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1. APPLICATIONS Multistage synchronous counting Multistage asynchronous counting Frequency dividers QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns SYMBOL...