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ON Semiconductor
ON Semiconductor
74HC14 Hex Schmitt-Trigger Inverter
74HC14

Hex Schmitt−Trigger
Inverter
High−Performance Silicon−Gate CMOS
The 74HC14 is identical in pinout to the LS14, LS04 and the HC04. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
The HC14 is useful to “square up” slow input rise and fall times. Due to hysteresis voltage of the Schmitt trigger, the HC14 finds applications in noisy environments.
Features
• Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input
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Philips
Philips
74HC14 Hex inverting Schmitt trigger
INTEGRATED CIRCUITS
DATA SHEET

74HC14; 74HCT14 Hex inverting Schmitt trigger

Product specification Supersedes data of 1997 Aug 26

2003 Oct 30

Philips Semiconductors
Hex inverting Schmitt trigger

Product specification
74HC14; 74HCT14

FEATURES
• Applications: – Wave and pulse shapers – Astable multivibrators – Monostable multivibrators.
• Complies with JEDEC standard no. 7A • ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. • Specified from −40 to +85 °C and −40 to +125 °C.

DESCRIPTION
The 74HC14 and 74HCT14 are high-speed Si-g
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NXP
NXP
74HC14 Hex inverting Schmitt trigger
74HC14; 74HCT14
Hex inverting Schmitt trigger
Rev. 7 — 19 November 2015

Product data sheet

1. General description
The 74HC14; 74HCT14 is a hex inverter with Schmitt-trigger inputs. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly changing input signals into sharply defined jitter-free output signals.
2. Features and benefits
 Complies with JEDEC standard no. 7A  Low-p
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Diodes
Diodes
74HC14 HEX INVERTERS
74HC14
HEX INVERTERS WITH SCHMITT TRIGGER INPUTS

Description
The 74HC14 provides provides six independent Schmitt trigger input inverters with standard push-pull outputs. The device is designed for operation with a power supply range of 2.0V to 6.0V.
The gates perform the Boolean function:
Y=A

Pin Assignments

Features
• Wide Supply Voltage Range from 2.0V to 6.0V • Sinks or Sources 4mA at VCC = 4.5V • CMOS Low Power Consumption • Schmitt Trigger Action at All Inputs • ESD Protection Exceeds JESD 22
ƒ 200-V Machine Model (A115-A) ƒ 2000-V Human Body Model (A114-A) ƒ Exceeds 1000
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NXP
NXP
74HC14-Q100 Hex inverting Schmitt trigger
74HC14-Q100; 74HCT14-Q100
Hex inverting Schmitt trigger
Rev. 4 — 19 April 2013 Product data sheet

1. General description
The 74HC14-Q100; 74HCT14-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A. The 74HC14-Q100; 74HCT14-Q100 provides six inverting buffers with Schmitt-trigger action. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 
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Sanyo Semiconductor
Sanyo Semiconductor
74HC145 LC74HC145









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Philips
Philips
74HC147 10-to-4 line priority encoder
INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT147 10-to-4 line priority encoder
Product specification File under Integrated Circuits, IC06 December 1990

Philips Semiconductors

Product specification

10-to-4 line priority encoder
FEATURES • Encodes 10-line decimal to 4-line BCD • Useful for 10-position switch encoding • Used in code converters and generators • Output ca
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National Semiconductor
National Semiconductor
74HC148 8-3 Line Priority Encoder
MM54HC148 MM74HC148 8-3 Line Priority Encoder

February 1988

MM54HC148 MM74HC148 8-3 Line Priority Encoder

General Description
This priority encoder utilizes advanced silicon-gate CMOS technology It has the high noise immunity and low power consumption typical of CMOS circuits as well as the speeds and output drive similar to LB-TTL
This priority encoder accepts 8 input request lines 0– 7 and outputs 3 lines A0–A2 The priority encoding ensures that only the highest order data line is encoded Cascading circuitry (enable input EI and enable output EO) has been provided to allow octal expan
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Fairchild
Fairchild
74HC148 8-3 Line Priority Encoder
MM74HC148 8-3 Line Priority Encoder

October 1987 Revised February 1999

MM74HC148 8-3 Line Priority Encoder
General Description
The MM74HC148 priority encoder utilizes advanced silicon-gate CMOS technology. It has the high noise immunity and low power consumption typical of CMOS circuits, as well as the speeds and output drive similar to LB-TTL. This priority encoder accepts 8 input request lines 0–7 and outputs 3 lines A0–A2. The priority encoding ensures that only the highest order data line is encoded. Cascading circuitry (enable input EI and enable output EO) has been provided to allo
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Hitachi
Hitachi
74HC148 8-to-3-line Octal Priority Encoder
HD74HC148
8-to-3-line Octal Priority Encoder

Description
The HD74HC148 encodes eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and enable output EO) is provided to allow octal expansion without the need for external circuitry. The data inputs and outputs are active at the low logic level.

Features
• • • • • High Speed Operation: tpd (0 - 7 to A0 - A2) = 15 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA 
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