74HC112; 74HCT112
Dual JK flip-flop with set and reset; negative-edge trigger
Rev. 4 — 11 January 2021
Product data s...
74HC112; 74HCT112
Dual JK flip-flop with set and reset; negative-edge trigger
Rev. 4 — 11 January 2021
Product data sheet
1. General description
The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to
voltages in excess of VCC.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
2. Features and benefits
Input levels: For 74HC112:
CMOS level For 74HCT112: TTL level
Asynchronous set and reset Specified in compliance with JEDEC standard no. 7A ESD protection:
HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information Type number Package
Temperature range
74HC112D
-40 °C to +125 °C
74HCT112D
74HC112PW -40 °C to +125 °C
74HCT112PW
Name SO16
TSSOP16
Description
Version
plastic small outline package; 16 leads; ...