MM74C86 Quad 2-Input EXCLUSIVE-OR Gate
October 1987 Revised January 1999
MM74C86 Quad 2-Input EXCLUSIVE-OR Gate
Genera...
MM74C86 Quad 2-Input EXCLUSIVE-OR Gate
October 1987 Revised January 1999
MM74C86 Quad 2-Input EXCLUSIVE-OR Gate
General Description
The MM74C86 employs complementary MOS (
CMOS) transistors to achieve wide power supply operating range, low power consumption and high noise margin these gates provide basic functions used in the implementation of digital integrated circuit systems. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swing essentially equal to the supply
voltage. No DC power other than that caused by leakage current is consumed during static condition. All inputs are protected from damage due to static discharge by diode clamps to VCC and GND.
Features
s Wide supply
voltage range: s Guaranteed noise margin: s High noise immunity: 3.0V to 15V 1.0V 0.45 VCC (typ.)
s Low power: TTL compatibility: Fan out of 2 driving 74L s Low power consumption: 10 nW/package (typ.) s The MM74C86 follows the MM74LS86 Pinout
Ordering Code:
Order Number MM74C86M MM74C86N Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Truth Table
Inputs A L L H H
H = HIGH Level L = LOW Level
Output B L H L H Y L H H L
Top View
© 1999 Fairchild Semiconductor Co...