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74AUP1G240 Datasheet

Part Number 74AUP1G240
Manufacturers NXP
Logo NXP
Description Low-power inverting buffer/line driver
Datasheet 74AUP1G240 Datasheet74AUP1G240 Datasheet (PDF)

www.DataSheet4U.com 74AUP1G240 Low-power inverting buffer/line driver; 3-state Rev. 01 — 6 November 2006 Product data sheet 1. General description The 74AUP1G240 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consump.

  74AUP1G240   74AUP1G240






Part Number 74AUP1G240
Manufacturers nexperia
Logo nexperia
Description Low-power inverting buffer/line driver
Datasheet 74AUP1G240 Datasheet74AUP1G240 Datasheet (PDF)

74AUP1G240 Low-power inverting buffer/line driver; 3-state Rev. 7 — 20 January 2022 Product data sheet 1. General description The 74AUP1G240 is a 1-bit inverting buffer/line driver with 3-state outputs. The device features an output enable (OE). A HIGH on OE causes the output to assume a high-impedance OFF-state. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the ent.

  74AUP1G240   74AUP1G240







Low-power inverting buffer/line driver

www.DataSheet4U.com 74AUP1G240 Low-power inverting buffer/line driver; 3-state Rev. 01 — 6 November 2006 Product data sheet 1. General description The 74AUP1G240 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP1G240 provides the single inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A HIGH level at pin OE causes the output to assume a high-impedance OFF-state. This device has the input-disable feature, which allows floating input signals. The inputs are disabled when the output enable input OE is HIGH. 2. Features s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114-D exceeds 5000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1.


2007-01-19 : 2SC2335    2SC5657    2SC838    5B38    74AHC594    74AHCT594    74ALVC162835A    74ALVCHT16835    74AUP1G240    74AUP1G97   


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