74ALVCH16952

INTEGRATED CIRCUITS 74ALVCH16952 16-bit registered transceiver (3-State) Preliminary specification Supersedes data of 1994 Jul IC24 Data Handbook 1998 Sep 01 Philips Semiconductors Philips Semiconductors Preliminary specification 16-bit registered transceiver (3-State) 74ALVCH16952 FEATURES Complies with JEDEC standard no. 8-1A CMOS low power consumption MULTIBYTETM flow-through pin-out architecture Low inductance, multiple center power and ground pins for minimum noise and ground bounce DESCRIPTION The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bi-directional busses. Data applied to the inputs is entered and stored on the rising edge of the clock (CPXX, where X is AB or BA) provided that the clock enable (CEXX) is LOW. The data is then present at the 3-State output buffers, but is only accessible when the output enable input (OEXX) is LOW. Data flow from A inputs to B outputs is the same as for B inputs to A outputs. Direct interface with TTL levels Output drive capability 50Ω transmission lines @ 85°C QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf = 2.5ns SYMBOL tPHL/tPLH fMAX CI CPD PARAMETER Propagation delay CPnn, to An, Bn Maximum clock frequency Input capacitance Power dissipation capacitance per buffer CONDITIONS VCC = 3.3V, CL = 50pF VCC = 2 2.5V, 5V CL = 30pF TYPICAL 3.2 350 3.0 UNIT ns MHz pF...