74ALVC125

INTEGRATED CIRCUITS DATA SHEET 74ALVC125 Quad buffer/line driver; 3-state Product specification 2002 Nov 18 Philips Semiconductors Product specification Quad buffer/line driver; 3-state FEATURES Wide supply voltage range from 1.65 to 3.6 V Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V) 3.6 V tolerant inputs/outputs CMOS low power consumption Direct interface with TTL levels (2.7 to 3.6 V) Power-down mode Latch-up performance exceeds 250 mA ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C. SYMBOL tPHL/tPLH PARAMETER propagation delay inputs nA to output nY CONDITIONS VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ VCC = 2.5 V; CL = 30 pF; RL = 500 Ω VCC = 2.7 V; CL = 50 pF; RL = 500 Ω VCC = 3.3 V; CL = 50 pF; RL = 500 Ω CI CPD input capacitance power dissipation capacitance per buffer VCC = 3.3 V; notes 1 and 2 outputs enable outputs disabled Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. DESCRIPTION 74ALVC125 The 74ALVC125 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced ...